Even though scanning electron microscopes (SEMs) have been sold for decades, their complexity warrants conservative choices in the electronics that are chosen. Although the complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuits (ASICs) have hundreds of input/output (I/O) elements, their exercise can be reduced to a handful of pins due to those ASICs having a joint test action group (JTAG) architecture, which would facilitate in-situ SEM analysis while exercising the part with a digital tester. With static transistors that have picoamp leakage currents or less, and dynamic leakage currents that are in the neighborhood of milliamps, all within a small time period e.g., 100 s of picoseconds, CMOS circuits will be responsible for large transient voltages, depending on the parasitic inductance associated with the interconnect.
Modern systems are extremely sophisticated, relying on state-of-the-art electronics to achieve performance only dreamed of just a few years ago. As the life cycle for state-of-the-art electronics becomes shorter and shorter, industry has become very concerned about long-term reliability, which is much more important to certain users e.g., airline industry, than the commercial market as a whole. This reliance on microelectronics has raised concern within high reliability manufacturers and consumers in the following areas: reliability of a stable supply of microelectronics; trust; reliability of microelectronic components; consistency in microelectronics components; and ability of a particular consumer or design entity to maintain its innovative ability.
Another not so obvious, but very important aspect of having microelectronic failure analysis capabilities in a trusted environment is the ability to design, manufacture and evaluate embedded security and other advanced concepts not possible otherwise. This work is often leading edge research and development, and does not necessarily require the most advanced foundry. Free access to microelectronic foundries enables a level of experimentation not possible otherwise absent an ability create new capabilities and experimentation options such as provided by embodiments of the invention.
The ramifications of this shift in microelectronic manufacturing location ripple through many critical aspects of the microelectronic used by industry. For example, the expertise and tools used by the foundries for failure analysis are the same as those used for assessing various aspects of suitability for use in trusted systems. These skills are critical for understanding the internal workings of microelectronic components. Significant risks are associated with a lack of visibility, a better understanding and enhanced ability to manipulate the internal characteristics of integrated circuits (ICs) that arise due to a lack of direct access to IC manufacturing plants or equipment. Aspects of the invention provide new abilities associated with investigation of highly complex IC systems relative to semiconductor physics, IC test/analysis Skills, digital test, but more importantly and less well understood, analog characteristics as digital circuits switch. Embodiments of the invention also provide ability to enable operation/innovative use of state-of-the-art IC test and failure analysis equipment and also provide ability to evaluate IC reliability to include failure mechanisms, analysis of test data, leading edge modeling, etc.
Signal or field measurement systems, such as a scanning electron microscope and/or oscilloscopes, can be designed to use utilize pixel sampling, averaging, and integration. These methods alone will miss features that are unique to the material being analyzed. Accordingly, there is an opportunity to improve signal or environment sensor analysis and representation. For example, by synchronizing a scan rate of a test system, such as a SEM electron beam with the in-situ clock rate of a CMOS circuit being analyzed in the SEM, signals from the Photo-Multiplier Tube (PMT), with voltages ranging from 0 to 5 volts, being monitored on an oscilloscope will experience maxima when the phase is adjusted, so that the excitation of transient secondary electrons will occur at the same time that transistors are switching. As phase is changed in time, maxima will occur, depending on the period of the switching transistors. A primary premise of one technique is that the elapsed time from secondary electron excitation to relaxation be of similar magnitude to the rise/fall time of the CMOS circuit. The transient secondary electron voltage effect will be greater for larger parasitic inductances of the interconnect and greater crowbar currents of the circuit.
In particular, it is possible to realize image or sensor enhancement that may not be readily observed by a normal offset sampling of a given pixel cycle. Since there can potentially be orders of magnitude more samples per pixel point, averaging, peak, offset, integration, max/min and custom algorithms can be acquired to realize image enhancement. A resulting image enhancement could then reveal unique features depending on the sample being analyzed. In one example, the sample interval to be processed could consist of a single cycle of the pixel clock, which could be accomplished by using a synchronized clock with the pixel clock. An embodiment of the invention can include system elements which provide for synchronization, monitoring signals from the PMT and phase adjustment which are then used, in part, to derive data used for image or measurement enhancement. Other possibilities for improvements are also possible in accordance with the invention.
One aspect of an inventive effort which in part produced this invention focused on a short and long term set of objectives. For example, once an exemplary scan rate of a SEM electron beam was synchronized with a clock rate of a CMOS device under test (DUT), a next step could include determining secondary electron behavior when a phase of the CMOS DUT clock rate is adjusted so that the secondary electron relaxation occurs at the same time that the CMOS DUT transistors are switching. A long term focus or objective of this effort was to develop a SEM technique for determining frequency behavior of electrical signals on metal interconnects and characterize the inductance of those interconnects as they pertain to CMOS circuits.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment exemplifying the best mode of carrying out the invention as presently perceived.